One of the goofier analogies I've seen...

[ericb@pobox.com (Eric M. Bennett)]

Some of these posts are truly funny for how dumb they are.  Others have
really powerful analogies like this one:


In article <dke-2110961726350001@adnline15468.adnc.com>
dke@adnc.com (David Every) writes:

> In article <54g51j$hqu@news-central.tiac.net>, dfield@tiac.net (David
> Field) wrote:
>
> | >Finally, the Pentium Pro incorporates many of the design features often
> | >found in a RISC chip, so it is somewhat misleading to refer to it as a
> | >CISC chip (despite Apple's insistence on doing it fairly often).
> |
> | No. The advantage of RISC is that there are no long instructions (The
> | first C in CISC stands for *Complex*) so there should be no decoding
> | of instructions to find out what they mean.
>
> Huh?
>
> RISC means reduced. This means that you simplify the instruction set so
> that you can use those gates for other things. At first this was for pipes
> and caches... now Intel can tack these on to their CISC design, but that
> doesn't make it RISC.  Its like putting a lawnmower engine in an old
> limosine and calling it a new economy car...


Eric Bennett ( ericb@pobox.com ; http://www.pobox.com/~ericb )
Cross-platform internet file format utilties at www.pobox.com/~ericb/xplat.html

The PowerTower Pro 225 from Power Computing calculates the 1024 points FFT
in a breath-taking 220 µs, whilst the fastest PentiumPro needs 2.78 ms for
it. . . . The result for the PowerStack from Motorola (with NT 4.0) of 0.95
ms looked 20% worse than for the equivalent Performa 6400. With
disassembling it was shown that Microsoft's C++ compiler left 15 of the the
PPC 603's floating point registers unused; the Metrowerks compiler for
MacOS, on the other hand, used all of them except two.
-Magazin Fur Computertechnik


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